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Online ISSN: 2578-3769


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Recognition and Visualization of Lithography Defects based on Transfer Learning
Authors: Bo Liu, Pengzheng Gao, Libin Zhang et al.
Institution:School of Information, North China University of Technology, Beijing
Keywords:transfer learning;neural network;lithography defects;visualize;Grad-CAM
Volume 3, Issue 3: 20030302, 2020 | PDF
Research Article
Published: Oct. 5, 2020
Abstract: Yield control in the integrated circuit manufacturing process is very important, and defects are one of the main factors affecting chip yield. As the process control becomes more and more critical ...
Study of Inverse Lithography Approaches based on Deep Learning
Authors: Xianqiang Zhang, Xu Ma, Shengen Zhang et al.
Institution:Key Laboratory of Photoelectronic Imaging Technology and System of Ministry of Education of China, School of Optics and Photonics, Beijing Institute of Technology, China
Keywords:Computational lithography;inverse lithography technology (ILT);optical proximity correction (OPC);deep learning
Volume 3, Issue 3: 20030301, 2020 | PDF
Research Article
Published: Oct. 7, 2020
Abstract: Computational lithography (CL) has become an indispensable technology to improve imaging resolution and fidelity of deep sub-wavelength lithography. The state-of-the-art CL approaches are capable o...
FinFET Performance Enhancement by Source/Drain Cavity Structure Optimization
Authors: Man Gu, Wenjun Li, Haiting Wang et al.
Keywords:FinFET performance;parasitic resistance and capacitance;source/drain cavity;cavity implant
Volume 3, Issue 2: 20030201, 2020 | PDF
Published: June 8, 2020
Abstract: Fin field-effect transistor (FinFET) technology has been introduced to the mainstream complementary metal-oxide semiconductor (CMOS) manufacturing for low-power and high-performance applications. H...
High-Pressure Oxidation on Ge: Improvement of Ge/GeO2 Interface and GeO2 Bulk Properties
Authors: ChoongHyun Lee
Institution:Zhejiang University
Keywords:High-pressure oxidation;Ge oxidation;High mobility channel;Ge/GeO2 interface;Interface trap density
Volume 3, Issue 2: 20030202, 2020 | PDF
Published: June 29, 2020
Abstract: On the basis of thermodynamic and kinetic consideration of Ge-O system, high-pressure oxidation (HPO) on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant ...
Volume 3, Issue 2: 20030203, 2020 | PDF
Research Article
Published: June 29, 2020
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...
DFM: “Design for Manufacturing” or “Design Friendly Manufacturing”
Authors: Wenzhan Zhou, Hung-Wen Chao, Yu Zhang et al.
Institution:Shanghai Huali Integrated Circuit Corp, China
Keywords:Design for Manufacturing (DFM);Design Friendly Manufacturing;EUV Lithography;Source Mask Optimization (SMO);Design Technology Co-optimization (DTCO);Process Window;Process Variation
Volume 3, Issue 1: 20030101, 2020 | PDF
Research Article
Published: March 30, 2020
Abstract: As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc.) pro...
Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing
Authors: Wei Zhang, Jun Xu, Sicong Wang et al.
Institution:Yangtze Memory Technologies Co., Ltd., Wuhan
Keywords:3D NAND;Metrology;Semiconductor;HAR;Process Control
Volume 3, Issue 1: 20030102, 2020 | PDF
Research Article
Published: March 30, 2020
Abstract: 3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a thr...
Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography
Authors: Yushu Yang, Yanli Li, Qiang Wu et al.
Institution:Shanghai IC R&D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, Shanghai
Keywords:5 nm Logic Process;EUV;metal gate cut;SAC;BAC;self-aligned LELE
Volume 3, Issue 1: 20030103, 2020 | PDF
Research Article
Published: March 30, 2020
Abstract: 5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pi...
A Study of 2D Assist Feature Placement
Authors: Liang Zhu, Barry Ma, Lin Shen et al.
Institution:Synopsys Inc., 1027 ChangNing Road, Shanghai, China, 200050
Keywords:Assist Feature;Inverse Lithography Technology;Low K1 Lithography;Machine Learning
Volume 3, Issue 1: 20030104, 2020 | PDF
Research Article
Published: March 30, 2020
Abstract: Sub-resolution assist features have been widely recognized in lithography patterning. In general, the insertion of assist features in optically adjacent space around main designed features, will ch...
A Device Design for 5 nm Logic FinFET Technology
Authors: Yu Ding, Yongfeng Cao, Xin Luo et al.
Institution:Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai
Keywords:5nm FinFET;brief process flow;key dimensions;simulated device DC/AC performance;RO PPA performance
Volume 3, Issue 1: 20030105, 2020 | PDF
Research Article
Published: March 30, 2020
Abstract: With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, N...