The architecture of process flow for FOPLP technology with die first based on chip face down was showed in Figure 2a. During this process, the back side thinned die with face down was attached on the surface of adhesive film which covered on the panel substrate. A molding process was introduced to form a protecting layer covering all the other five sides of chip (except the top side) with solid or liquid epoxy molding compound (EMC) material. The thickness of EMC was usually twice of the chips. After a curving process of EMC, a new panel sample with same size to the panel substrate was formed. The panel substrate and the adhesive film were all removed from the new panel sample. Two patterning passivation (PA) layers and two patterning re-distribution (RDL) layers were interleaving and overlapping with each other on the surface of the new panel sample. The number of the PA layer and RDL layer were usually all two, and the patterning RDL2 layer located on the surfaces of PA2 layer and connected with RDL1 layer through the opening area in PA2 layer. Finally, the solder ball was formed on the RDL2 layer and the new panel sample was sawed into chips.

The architecture of process flow for FOPLP technology with die first based on chip face up was showed in Figure 2b. During this process, the back side thinned die with a pre-connected copper (Cu) bump on its aluminum (Al) pad was attached on the panel substrate withing face up. A molding process was introduced to form an insulation layer with the chips all embedded in the EMC layer. The thickness of EMC layer was usually more than twice of the chips. After a curving process of EMC, a new panel sample with same size to the panel substrate was formed. Then the EMC was thinned to the appearance of the Cu bump which connected on the Al pad of chip. The substrate and the adhesive film were all removed from the back side of the new panel sample. Two patterning RDL layers and one patterning PA layer were interleaving and overlapping with each other on the surface of EMC layer, and the patterning RDL2 layer located on the surfaces of PA1 layer and connected with RDL1 layer through the opening area in PA1 layer. Finally, the solder ball was formed on the RDL2 layer and the new panel sample was sawed into chips.

The architecture of process flow for FOPLP technology with RDL first was showed in Figure 3. During this process, a patterning RDL was formed on the panel substrate, then the chip with a pre-connected Cu bump on its Al pad was connected to the patterning RDL on the panel substrate with flip chip technology. A molding process was introduced to form a protecting layer with the chips all been covered in the EMC layer. The thickness of EMC layer was usually twice of the chips. After a curving process of EMC, a new panel sample with same size to the panel substrate was formed. The substrate and the adhesive film were all removed from the back side of the new panel sample. The EMC layer acted as the PA1 layer and the RDL layer formed on the substrate acted as the RDL1 layer for the FOPLP device. Then another one PA layer and another one RDL layer were interleaving and overlapping with each other on the surface of EMC layer and RDL1 layer. The patterning RDL2 layer located on the surfaces of PA2 layer and connected with RDL1 layer through the opening area in PA2 layer. Finally, the solder ball was formed on the RDL2 layer and the new panel sample was sawed into chips.

3.3 Comparison between die first and RDL first process

Die first and RDL first were two core process flows for FOPLP technology, which could be suitable for different scenarios. The process flows of die first and RDL first were also described in the above parts. While, based on the difference between die first and RDL first, there are several comparative analysis including process flow, technical characteristics, applicable scenarios and technical challenges were described in the follow part.^[54] First, for the comparison of process flow, the die first had a process flow in order of chip attachment, modeling, RDL fabrication, ball planting and cutting. While, the RDL first had a process flow in order of RDL fabrication, chip inversion, modeling and debonding, ball planting and cutting. Second, for the technical features and advantages, the die first had advantages of simple process and wide applicability. While, the yield challenge and design limitations were also the main limitations for die first process. For RDL first process, it had the advantages of high yield, high density interconnection and warpage controlling. RDL first process also had the limitations of complex process and thermal management challenge. Third, for the applicable scenarios, chips packaged in die first process were mainly focused on mid to low end applications, such as consumer electronics (PMIC, RF modules), which had high cost and design flexibility requirement. Die first process was also widely used in single chip packaging, which was suitable for scenarios with fewer pins and wider line width and spacing. While, chips packaged in RDL first process were mainly used in high end applications, such as server CPUs and AI accelerators, which was usually required with high-density interconnection and low signal latency. The multi chip heterogeneous integration (such as CPU+GPU+HBM) and vehicle grade chips (requiring high reliability and high temperature resistance) were also packaged in RDL first process. Fourth, for the technical challenges, the chip first process had the die shift (or chip offset) and warpage problem, which were mainly caused by the liquid flow and mismatch between coefficient of thermal expansion (CTE) during the encapsulation process. While, the RDL first process also had the technical challenges of material compatibility for matching CTE between low loss dielectric materials and highly conductive metals to reduce internal stress. The process complexity of high precision lithography and electroplating equipment are also required in RDL first process, resulting in a high manufacturing cost.

In terms of size specification, the size of square plate has been always increasing. At present, the size of square plate included 300x300mm, 510mmx415mm, 515mmx510mm, 600mmx600mm, 615x625mm, 620mmx750mm, 700mmx700mm, 800x600mm, 800x800mm. Although a large size square plate had a lower cost, but a larger size square also caused substrate warpage easier, which will cause the accuracy and die shift, all those would all have an adverse effect on the yield issues. The die shift of dies caused during the modeling process had brought a very serious problem for the RDL distribution. The architecture of die shift forming during the modeling process was showed in Figure 4a. The EMC with a flowing state would generate impact forces on the die attached on the panel with adhesive film from all directions. The impact forces focused on the die were incommensurate, which caused die shift, thus leading a re-layout mapping for RDL layer covered on the surface of EMC layer.

For the root cause of die shift during the modeling process, there were main three reason including mechanical stress mismatch, influence of EMC flow and limitation of process accuracy. For the mechanical stress mismatch, there is a significant difference in the coefficient of thermal expansion (CTE) between chips and EMC, which generated internal stress during the process of high-temperature curing or cooling, resulting in a displacement of chip position. For the influence of EMC flow, it will exert dynamic fluid pressure on the chip during the filling process by EMC in liquid, which can drive chip displacement and resulting in a die shift. For the limitation of process accuracy, the insufficient accuracy of chip placement equipment can directly lead to initial position deviation and amplify the error in subsequent process.

Meanwhile, every die caused a different die shift during the modeling process, which caused every chip also to need a specific first RDL layer distribution for meeting its electrical requirements. During the modeling process, the ideal situation for the distribution of chips was showed in Figure 4b, every die was still attached on the panel and packaged by EMC in a very orderly distribution, and die 1 to die 4 all had no die shift. While, die 11 to die 44 all had different die shift caused by impact forces of flowing EMC during the modeling process. As showed in Figure 4c, die 1 had a turning right shift in horizontal direction, the die 2 had a turning up shift in vertical direction, the die 3 had a rotating shift in clockwise. While, the die 4 had a modular die shift composed of die shift in vertical direction & vertical direction & rotating. In other words, dies embed in EMC layer had different die shifts during the modeling process.

For the various die shift caused during the modeling process, the first RDL layer covered on the EMC layer was a very complex distribution. To solve this thorny issue, an automated optical inspection (AOI) process was introduced to confirm the position of each pad on every die with various die shift, then a new RDL distribution mapping was created based on the AOI result. The RDL layer was formed following the new first RDL layer distribution mapping completely. As showed in Figure 5a, without any die shift, the first RDL layer distribution for each pad around the die was same completely, and the end point of first RDL layer distribution for each pad was fixed. While based on the various die shift caused during the modeling process, the AOI process and the new first RDL layer distribution mapping was introduced to cover the various die shift of every pad around die embedded in EMC layer. As showed in Figure 5b, without correction of die shift, the first RDL layer distribution for each pad around the die was various, and the end point of the first RDL layer distribution for each pad was random. As showed in Figure 5c, with a correction of die shift, the first RDL layer distribution for each pad around the die was various, but the end point of the first RDL layer distribution for each pad was also fixed. Compared with Figure 5a, the end point of the first RDL layer distribution for each pad as showed in Figure 5c was no changed, thus could guarantee the patterning of next passivation layer and RDL layer distribution follow the originally designed without any changed.

For the FOWLP technology, the warpage of wafer occurred during packaging process due to the accumulation of thermal and mechanical stress, which could reduce the process accuracy of subsequent mask lithography and limits the improvement of rewiring layer density. For FOPLP technology, with the increasing of panel size, the warpage of panel was more significant than that of FOWLP technology, thus leading the packaging process being cut off during the process which needed a high flatness, such as the PVD and lithography processes. The stress generated by warpage was easily concentrated at the intermediate layer or solder joint, causing the solder ball to crack and fall off, and the intermediate layer to delaminate. For FOPLP technology, the main reasons for the panel warpage were widely recognized by the curing of EMC materials and the mismatch of coefficient of thermal expansion (CTE) of different materials. Besides, there were many other reasons been found that could also affect the panel warpage, those reason included the anisotropy of silicon, the viscoelastic relaxation effect of EMC, the process steps after curing, especially in processes with drastic temperature changes such as rewiring and ball planting, as well as gravity and other factors. The larger the panel size was, the more significant the warpage formed. With the application of large-sized panel in fan out panel level packaging, the warpage of panel had become a prominent issue restricting the development of FOWLP. In order to minimize the impact of panel warpage as much as possible, a planarization process was introduced followed by every curving process. The flatting effect can almost coverage the negative effect caused by the panel warpage.

For the root cause of panel warpage during the whole packaging process, there were main three reason including uneven distribution of thermal stress, material anisotropy and insufficient uniformity of the process. For the uneven distribution of thermal stress, the panel (such as glass or organic substrate) and modeling material will generate asymmetric thermal stress due to different CTE during high temperature process, resulting in overall deformation of the panel. For the material anisotropy, the residual stresses created after cooling process based on the dis-match between the mechanical properties of the panel (such as rigidity) and the flexibility of modeling material. For the insufficient uniformity of the process, uneven modeling thickness or curing rate of large size panels (such as 600x600mm) can also exacerbate part warping.

In terms of RDL for FOPLP technology, the line and space width have currently reached 10um/10um, but there are also manufacturers ranging from 5um to 2um. There is a trend in the future to follow the same process as wafer level packaging, and may even break through the physical limitations of panel level packaging to 1um. If we can truly have a mass production of 5um-5um, the related technology will be sufficient to expand to more high-end applications with performance, heat dissipation, and efficiency requirements, especially the multi-chip and heterogeneous integration of active and passive devices. To achieve higher resolution in FOPLP, a high-density RDL with line and space width of 5um or less still needs to overcome technical challenges in the future. Large scale substrates faced various challenges in handling warped carriers such as glass, stainless steel, and polymers for precise movement. In the developing of FOPLP technology, how to achieve uniform etching rate and large-area electroplating uniformity on large-area substrates with line/space width ranging from 20um/20um to 15um/15um, and then to 10um/10um is still a huge challenge.

4.4 Innovative improvement methods for FOPLP challenges

As described in above three parts, there are three mainly challenges existed during the whole FOPLP technology including die shift, panel warpage and RDL process capability, which have impeded the rapid expansion of FOPLP technology in IC packaging industry. For solving those impediment of FOPLP technology, many efficiency strategies have been proposed.

As it was known that the die shift was mainly caused by a chip displacement, which was caused by the dynamic fluid pressure from the liquid EMC during the filling process of modeling. There are many technologies have been tried to reduce the die shift of chip during modeling process, and a few basic theoretical of the solution have been given out, such as optimization of material matching, process control technology and optimization of structural design. For the optimization of material matching, there are two strategies including developing EMC which had a CTE similar to chip and using low modulus modeling material to absorb stress through elastic deformation for reducing mechanical impact on chips. For the process control technology, the strategies of adaptive patterning and low temperature curing process are the mainly methods. For adaptive patterning technology, chip position can be corrected in real time through laser scanning and the offset trends of chip can also be predicted by combining with Al algorithms. For low temperature curing process, the stress accumulation caused by CTE differences can be retard obviously by reducing curing temperature of EMC. For the optimization of structural design, the common used method is by using temporary bonding adhesive to fix the chip and reduce interference from the flow of EMC during modeling process. For reducing the chip displacement and limiting the moving range of chip during the modeling process, J. Liu^[55] has proposed three ideas for decreasing the die shift, including the groove type modeling structure, penetrating type modeling structure and photoresist cofferdam type packaging structure. As showed in Figure 6. For the groove type modeling structure, the related process was showed in Figure 6a. The panel with mult groove type structure was formed during modeling process by using a special molding mold. Then chips with adhesive film pasted on its backside was attached in the groove in panel. It must be noticed that the size of groove was a little larger than chip. Finally, a PA layer was by using dry film based on the vacuum pressing technology. Limited by the groove type structure of EMC, the chip will not caused a great die shift during the formation of PA layer. For the penetrating type modeling structure, the related process was showed in Figure 6b. The panel with mult penetrating type structure was formed during modeling process by using a special molding mold. Then the adhesive layer and panel with mult penetrating type structure were attached on a substrate sequential, which can also form mult new groove type structures. Chips were attached in the new groove type structures in panel. The size of penetrating type structure was also a little larger than chip. A PA layer was also formed by dry film based on the vacuum pressing technology. The chip will also get a little die shift during the formation of PA layer. For the photoresist cofferdam type packaging structure, the related process was showed in Figure 6c. The photoresist was used to form cofferdam on the substrate with adhesive film. Chips were attached in the cofferdam on substrate. The size of cofferdam was a little larger than chip, then a modeling process was introduced to form panel by forming EMC layer and also fix chips on substrate . After separating the adhesive film and substrate from EMC layer, the cofferdam structure forming by photoresist was also removed from the surface of EMC layer. Finally, a PA layer was formed by dry film based on the vacuum pressing technology. Being limited by the photoresist cofferdam, the chip can not get a great die shift during modeling process.

For reducing the influence of panel warpage, the basic theoretical of the solution mainly included material innovation, simulation and optimization of process, improvement of equipment and process. For the material innovation, there are two strategies of glass substrate replacing organic substrate and the introduction of high thermal conductivity modeling material. The CTE of glass (about 3ppm/℃) is closer to that of silicon (2.6ppm/℃), and it also has excellent thermal stability, which can all reduce the panel warpage significantly. By introducing aluminum nitride (AlN) or graphene filling materials could improve the efficiency of heat dissipation and reduce deformation caused by thermal gradients. For the simulation and optimization of process, finite element analysis (FEA) and designing symmetric structure are common methods to reduce the panel warpage. The FEA can predict the trend of panel warpage and optimize modeling parameters (such as temperature curves and pressure distributions) through thermal mechanical coupling simulation. Adopting a symmetrical chip layout in the panel layout can balance thermal stress distribution and reduce asymmetric deformation obviously. For the improvement of equipment and process, the effective methods for reducing panel warpage includes double sided modeling technology and progressive curing process. Applying modeling layer on both sides of panel in simultaneously can also counteract single-sided stress. Meanwhile, controlling the curing temperature and time in stages for releasing material stress gradually can also reduce panel warpage obviously.

For improving the RDL process capability of FOPLP technology, the core improving direction mainly included the upgrading of high-density cabling technology and the optimization of plating and etching processes. For the upgrading of high-density cabling technology, the RDL first process and hybrid lithography technology can all improve the RDL process capability. By prioritizing the formation of RDL layer on the carrier before attaching chips can support finer line/width distances (such as 5um/5um). Meanwhile, by combining stepper lithography equipment with laser direct writing equipment, it can solve the problem of decreased resolution at the edges of large-sized panel effectively, resulting in the uniformity of RDL line width at ±0.5um on panel of 600x600mm. For the the optimization of plating and etching processes, the cup type vertical plating technology developed by Manz Group could achieve the uniformity of plating large than 90% by multi zone anode zone designing. The application of dry film photoresist can reduce bubble defects and support copper pillar structures with higher aspect ratios. The concepts of emerging process and integrated solutions for improving the RDL process capability of FOPLP technology mainly included the fusion of heterogeneous integration technology and intelligent process control. The strategies of fusion of heterogeneous integration technology included the collaborative design of TSV+RDL and the integration of glass substrate. The optimization of AI dynamic parameter and the system of real time deformation compensation can all realize the control of intelligent process. For example, Huatian Technology had increased the yield of RDL lamination process from 75% to 92% by using machine learning to simulate the combinations of material thickness, curing time and other parameters.

During the process of FOPLP packaging, many organic materials were used in the process of IC packaging. For example, the EMC was introduced to fix chips for forming panel sample in FOPLP technology, the dry film was introduced to form passivation layer by vacuum pressing technology for protect chips and RDL layers, the PSPI was also introduced to act as the passivation layer to guarantee the normal function of chips, the PR was introduced to help forming RDL. In this chapter, the author introduced the application of organic materials mentioned above in detailly.

EMC is a thermosetting chemical material with using in semiconductor packaging. The EMC refers to a type of polymer that contains two or more epoxy groups in its molecules, which main contains epoxy resin, hardener, silica, and other additives.^[56] Epoxy resin was originally formed by the condensation of epichlorohydrin and bisphenol A, and now epoxy resin is usually formed by the low molecular weight diglycidyl ether of bisphenol A and various modifications, thus leading epoxy resin having various thermosetting structures and curing agent changes.^[57] The global manufacturers of epoxy packaging materials for semiconductors mainly include Sumitomo Bakelite, Showa Denko, Panasonic, Kyocera, Shin Etsu Chemical, Chang Chun Group, KCC, Samsung SDI, Nagase ChemteX Corporation and Hysol Huawei Electronics.^[58] The top ten global manufacturers hold approximately 63.0% of the market share in 2022.

The EMC is a thermosetting material composed of epoxy resin, curing agent, curing accelerator, filler and other modified components. Since the development of epoxy molding materials, many different types have been derived to meet different application requirements. According to the chemical structure of the epoxy resin used, the EMC can be divided into EOCN type, DCPD type, Biphenyl type and multi-Function type. According to the performance of the final material, epoxy molding materials can be divided into ordinary type, fast curing type, high thermal conductivity type, low stress type, low radiation type, low warpage type and no post curing type. Figure 7 showed the molecular structures of the main epoxy resins types used in epoxy molding compounds. Different types of epoxy molding compounds are suitable for different semiconductor packaging forms. We can characterize and measure the properties of EMC by using some physical parameters, such as gelation time, flow length, viscosity, flexural strength, flexural modulus, glass transition temperature (Tg), thermal expansion coefficient, water absorption, molding shrinkage, thermal conductivity, volume resistivity, dielectric constant, ion content, flame retardancy and so on. The EMC material usually had high mechanical and electrical properties, good coloring properties and excellent heat resistance. l properties, good coloring properties and excellent heat resistance. The performances of three typical EMC were listed in Table 2.

The key properties of EMC mainly include thermal performance, electrical performance, mechanical properties, chemical stability, liquidity and filling capacity, curing speed and reactivity. ^[59] For the thermal performance, it is necessary for EMC to have good thermal stability and be able to maintain its performance in high temperature environments. For example, there is no causing damage for chips or packaging materials due to excessive stress in lead-free reflow soldering at 260℃. For electrical performance, EMC should also have good electrical insulation and dielectric constant to prevent the electrical performance of chips from being affected by the external environment. For the mechanical property, it is required for EMC to have good bending strength and bending modulus to withstand the bending and pressure during the packaging process. Good adhesion and wire resistance are also necessary to ensure a strong bond between the chips and the packaging materials. For the chemical stability, EMC should have good water resistance and low water absorption to prevent electrical faults caused by moisture. For the liquidity and filling capacity, Epoxy sealant should have good fluidity, which could be able to evenly fill the mold and avoid voids or defects during the packaging process.^[60] For the curing speed and reactivity, EMC should have a fast curing speed and good reactivity, which could guarantee that the curing process can be completed quickly during production.

The types of epoxy resins are mainly including bisphenol A-type epoxy resin (DGEBA), bisphenol F-type epoxy resin (DGEBF), phenolic epoxy resin (Novolac), brominated epoxy resin, cycloaliphatic epoxy resin, water based epoxy resin and modified epoxy resin.^[61] The typical application cases of those epoxy resins mentioned above were listed as below. The DGEBA was usually used for the reinforcement of building structure (such as bridge repairing) based on its high adhesive strength (>20MPa) and mechanical properties, also with a curing shrinkage rate of only 1-2%. The extended application of DGEBA was used as electronic packaging substrates (such as PCB laminates), which could ensure signal transmission stability by utilizing its low dielectric loss. The DGEBF was usually used as ship anti-corrosion paint. By combining with polyamide curing agent, DGEBF could achieves a low-temperature (5℃) construction in wet surface. The Novolac was usually used in the preparation of high frequency and high-speed PCB substrate (such as 5G base station circuit board). The high cross-linking density of Novolac is contribute to a glass transition temperature (Tg) of over 170℃, and its heat resistance is superior to that of ordinary resins. The typical application cases of brominated epoxy resin was acted as the flame retardant cable sheath for data centers, which can suppress the arc propagation to ensure fire safety in the computer room under short-circuit conditions. For the cycloaliphatic epoxy resin, the typical application case was used as the packaging adhesive for outdoor LED, which was based on its increasing three times UV aging resistance determined by the structure without benzene ring. While, the typical application case of water based epoxy resin was used as floor coating for food factories. After solidification, the surface hardness of water based epoxy resin layer is greater than 4H, which can also be resistance for the repeatedly scrubbing of acid alkali cleaning agents. The application case for modified epoxy resin case mainly included the silicone modified type epoxy resin and polyurethane modified type epoxy resin, which were used as the structural adhesive for curtain walls of super high-rise buildings and the protective coating of wind turbine blade leading edge.

As a new introduced packaging material, the MEC prevented chips from being impacted by covering electronic components such as inductors, connectors and power supplies, as showed in Figure 8. More than 90% of electronic components were covered with EMC material based on the IC advanced packaging and the used EMC material usually required with low warping, low expansion, high filling and high thermal conductivity.

To solve the problems of irregular printing and bubbles causing a decrease in yield during liquid resin coating, controlling the thickness of conductor in free and the elimination of steps such as removing copper foil in the semi additive process, the dry film was introduced in IC packaging based on its advantages comparing to the liquid resin.^[62] The dry film was usually covered on the wafer or panel by the vacuum pressing technology. Photosensitive dry film was usually introduced as passivation layer during the process of FOPLP technology, as showed in Figure 8. For the photosensitive dry film, it usually consists of polyethylene film (PE), photoresist film and polyester film (PET). The structural composition of photosensitive dry film was showed in Table 3. The PE film serves as the carrier for the photosensitive layer, used for coating mixed photosensitive materials into a film. The PET film is the protective layer of photosensitive dry film, mainly used to isolate oxygen, avoid delamination and mechanical scratches. Among the three parts, the photoresist film also known as the photosensitive layer, is the most important component of the photosensitive dry film, mainly composed of photosensitive materials for photolithography. The alkali soluble resin serves as a film-forming agent for photosensitive dry films, bonded the various components of the photosensitive adhesive to form a film and acted as a pseudo skeleton for corrosion resistance.^[63]

The photopolymer monomer created polymerization reaction under ultraviolet light irradiation and generated a polymer, thus leading the photosensitive part does not fuse with the developing solution and forming a corrosion-resistant image.^[64] During the exposure process, the photoinitiators absorb the energy of ultraviolet light to generate free radicals, which trigger crosslinking of photopolymerization monomers. After the initiated polymer monomer polymerization reaction occurs, a fine pattern with a resolution of 10-40um needs to be formed on the dry film, so the distribution ratio of each material component in the photosensitive layer is extremely high. For the alkali soluble resin, Cuihong Zhang^[65] had reported an alkali-soluble polyimide resin, which was obtained by chemical reaction in a mixed solution with 4,4 '- diphenyl ether dianhydride (ODPA), 2,2-bis (3-amino-4-hydroxyphenyl) hexafluoropropane (BAHF), 1,3-bis (3-aminopropyl) tetramethyldisiloxane (SiDA) and 3-aminophenol (MAP), the synthetic route of alkali-soluble polyimide resin was showed in Figure 9. The main components and suppliers of photoresist film were showed in Table 4, the alkali soluble resin was usually made by blending methyl methacrylate and butyl acrylate and ethyl acrylate, and the suppliers included Mitsui Chemicals, Mitsubishi Chemical and Dow Chemical. The photopolymer monomer was usually made up of glycerol propoxylate, ethoxynonylphenol acrylate, and the suppliers included Mitsubishi Chemical and MARUBENI Corporation. The photoinitiators was usually made up of N-phenylglucosamine, diphenyl-1,1-diimidazole and 4,4-bis (diethylamino) benzophenone, the suppliers included BASF and MARUBENI Corporation.

The typical dry film used in IC packaging mainly included the anti corrosion dry film, the high resolution photosensitive dry film, the mask dry film and the solder mask dry film, and the application case of those dry films were introduced as below.^[66] For the anti corrosion dry film, which was mainly used as pad protecting layer in ball grid array (BGA) packaging and pin graphing layer in four sided flat package (QFN) packaging. When using as pad protecting layer in the packaging process of BGA, the anti corrosion dry film served as a corrosion-resistant layer to protect the copper layer in non solder areas, avoiding the penetration of plating solution during the formation of solder balls. When using as pin graphing layer in the packaging process of QFN, the pins of QFN without pins are transferred to high-precision patterns through anti corrosion dry film lithography technology and formed the bottom heat dissipation pads and electrodes. For the high resolution photosensitive dry film, which was usually introduced in the fabrication of micro bump in the packaging process of flip chip (FC) and the redistribution of line in FO packaging.^[67] In the packaging process of FC technology, the high resolution photosensitive dry film is used for lithography to form micrometer sized copper pillar protrusions and achieve vertical interconnection between chip and substrate. The high flexibility of high resolution photosensitive dry film could also reduce the risk of graphic breakage after the development process during lithography. During the packaging process of FO technology, the high resolution photosensitive dry film is usually used to make redistribution layers (RDL), which could extend chip pins to a larger area on substrate. The typical application case of mask dry film mainly included acting as the hole protecting layer in through silicon via (TSV) packaging and the solder ball mask for chip scale packaging (CSP). The mask dry film was usually used as temporary protection layer of the inner wall in TSV hole to prevent plating solution from contaminating the silicon substrate in 3D stacked packaging. The mask dry film was also used as a mask to limit the position of solder balls and increase packaging density in CSP.^[68] While, for the typical application case of solder mask dry film, it was usually included the insulation protection layer of automotive electronic module packaging and heat dissipation enhancing layer of power device packaging. When used as a packaging solder mask for engine control modules (ECUs), solder mask dry film was capable of withstanding high temperature and high humidity environments (85℃/85% RH). The solder mask dry film was also combined with metal substrate to optimize the heat dissipation path in IGBT module packaging, which could resist electrochemical migration and prolong device lifetime.

During the process of FOPLP technology, the PA layer formed by organic material was usually introduced to cover on the RDL layer. The number of PA layer was usually more than one layer, which was decided by the technological requirements of FOPLP technology. With the development of technology, PSPI was usually used as PA layer in the FOPLP technology, as showed in Figure 8. Compared to traditional photoresists, PSPI had no requirement on the application of light blocking agents and could significantly reduce processing steps. Meanwhile, PSPI also played an important role as buffer coatings and radiation shielding materials and interlayer insulation materials. PSPI had two main applications of photoresist and electronic packaging. Compared to traditional photoresists, PSPI had no requirement on the application of light blocking agents and could significantly reduce processing steps. Meanwhile, PSPI also played an important role as electronic packaging adhesive, and PSPI was also used as a packaging material for buffer coatings, passivation layers and radiation shielding materials, interlayer insulation materials, chip packaging materials. PSPI were also widely used in the microelectronics industry, including packaging of integrated circuits and multi-chip packaging components. In currently, there are many companies have developed PSPI materials, such as Toray Industries, Inc., Fujifilm Electronic Materials, HD Microsystems, Kumho Petrochemical, Asahi Kasei Corporation, Eternal Materials, JSR Corporation and Merck. The global leading companies and market share in PSPI was listed in Table 5, the three biggest companies of PSPI in market share were Toray Industries, Inc., Fujifilm Electronic Materials and HD Microsystems, the values of their market share were 78%, 5.7% and 4.8% respectively. A few Chinese companies have also carried out PSPI related business, which included Jilin Optical and Electronic Materials Co., Ltd., Jiangsu Sunera Technology Co., Ltd. and Hubei Dinglong Co., Ltd.

Traditional positive photoresist is mainly composed of three parts: film-forming agent (linear phenolic resin), photosensitive agent and solvent, which have good photosensitivity. In the molecular design of positive PSPI, it is expected to become soluble in the exposed area, which can be washed away during the development process. Meanwhile, the un-exposed area can also form a patterning during the development process. For reaching this purpose, some functional groups such as carboxyl groups which can be dissolved in dilute alkaline solutions were usually introduced into PI. Some PI dissolution inhibitors that can be decomposed when exposed to light, such as diazonaquinone sulfonate compounds were also added into PI for the preparation of PSPI. PSPI photoresist can be classified into positive and negative photoresist based on the imaging mechanism of the photoresist sample. PSPI photoresist can also be classified into G-line/I-line/mixed line photoresist based on the exposure wavelength. Different types of PSPI photoresists have significant differences in resin selection, and are often subdivided into various types such as negative ester type PSPI, negative ion type of PSPI, positive diazonaphthoquinone (DNQ) type of PSPI, chemical amplification type of PSPI and so on, as showed in Figure 10. For the negative ester type PSPI, the photosensitive group was connected to the polyimide prepolymer with ester bonds, as showed in Figure 10a. For the negative ion type of PSPI, the PAA resin was obtained by reacting with organic amine compounds to form salts, as showed in Figure 10b. For positive DNQ type of PSPI, the ortho azide naphthoquinone group was introduced with side groups or directly added to impart photosensitivity, as showed in Figure 10c. For the chemical amplification type of PSPI, which was usually composed of photo induced acid generator (PAG, such as PTMA) and matrix resin (PAA), as showed in Figure 10d. Under the UV irradiation, the PAG can decompose into super strong acid, then catalyzing the decomposition or crosslinking reaction of matrix resin. Due to its recyclability, it has high efficiency and therefore has a chemical amplification effect.

In currently, PSPI has become a key material in IC advanced packaging due to its unique photosensitivity, high heat resistance, low dielectric constant and excellent mechanical properties.^[69-70] For the typical application case of PSPI, there are mainly four aspects which were described as below. Firstly, PSPI was usually used as stress buffering and insulation layer in IC advanced packaging technology, such as BGA/CSP/wafer level packaging (WLP).^[71] For example, the PSPI products developed by Bomi Technology are widely used as surface passivation layers and stress buffering layers in BGA packaging, CSP packaging and WLP packaging. PSPI usually had a few excellent characteristic such as high heat resistance (glass transition temperature ≥150℃), low shrinkage rate (curing shrinkage rate ≤0.5%) and high mechanical strength (shear strength ≥80MPa), which could meet the stringent requirements of high-frequency vibration and temperature cycling.^[72-73] Secondly, PSPI was also used as high density interconnection in WLP packaging. For example, PSPI was used as an interlayer medium layer in 3D IC stack packaging to ensure the stability of high-density interconnection. Tongfu Microelectronics and other packaging enterprises also have achieved precise lithography of micrometer level circuits to support 2.5D/3D packaging technology requirements by using PSPI. Thirdly, PSPI was also used to meet the low temperature curing requirement of chips in 2.5D/3D packaging. The low temperature process compatibility of PSPI with a low curing temperature was compatible with traditional packaging materials (such as epoxy resin) processes, which can reduce energy consumption effectively.^[74] Fourth, PSPI was also used in packaging process of optical communication modules and high-performance computing chips. When used as the packaging insulation layer for optical communication chips, its high insulation (volume resistivity ≥1×10¹⁶Ω· cm) and low moisture absorption (water absorption rate ≤0.5%) ensured the long-term reliability of optoelectronic devices. When used in packaging process of high bandwidth memory (HBM) and logic chips, the high thermal conductivity (≥1.5W/(m·K) of PSPI can reduce the thermal resistance and improve the heat dissipation efficiency of devices.

Photoresist generally consists of four parts, including resin type polymer, photosensitive agent, solvent and additives. The resin type polymer is an inert polymer matrix used as an adhesive to bring together different materials in photoresist. The resin type polymer also gave the mechanical and chemical properties of photoresist, such as adhesion, flexibility and thermal stability. The resin type polymer is insensitive to light and does not undergo chemical changes after exposure with ultraviolet light. The photosensitive agent is a photosensitive component in photoresist, which could react with radiation energy in the form of light, especially in the ultraviolet region. The solvent keeps the photoresist in a liquid state for allowing it to be applied onto the silicon wafer substrate. The additives are used to control and alter specific chemical properties or photoresponsive characteristics of photoresist. At present, the core technology of semiconductor photoresist is basically monopolized by Japanese and American companies, including JSR, TOK, ROHMHAAS, ShinEtsu and FUJIFILM. The market share of photoresist in global for JSR, TOK, ROHMHAAS, ShinEtsu and FUJIFILM were 28%, 21%, 15%, 13% and 10%, respectively. The semiconductor photoresist has the highest technological content and is the most expensive material. According to the exposure wavelength, the semiconductor photoresist can be divided into five categories, the g-line (436nm), the i-line (365nm), the KrF photoresist (248nm), the ArF photoresist (193nm) and the EUV photoresist (13.5nm), as showed in Table 6. The ArF photoresist and EUV photoresist were mainly used for 12 inches wafer, and the g-line photoresist/i-line photoresist/KrF photoresist were mainly used for 6 inches or 8 inches wafer. Among them, ArF photoresist is the highest resolution semiconductor photoresist in currently. The g-line and i-line photoresist are currently the most widely used photoresist in the market.

Photoresist has played a crucial role in IC advanced packaging technologies, its high-precision patterning ability, material compatibility and process adaptability have become core technologies for improving packaging density and reliability. The typical application cases and characteristic analysis of photoresist used in IC advanced packaging were listed as below. Firstly, photoresist was used in the graphization of high-density RDL. For example, photoresist was used to fabricate fine lines for RDL in 2.5D/3D IC packaging, the high resolution of photoresist can guarantee the formation of micrometer level lines through photolithography process to meet high-density interconnect requirements. Meanwhile, the process compatibility of photoresist could support with multiple substrate materials (such as silicon interlayer and organic substrate) by compatible with heat curing or UV curing processes. Secondly, photoresist was used for the formation and precise positioning of solder bumps. In related patented technology, photoresist was used to define the position of solder bumps by two photolithography patterning processes (first photoresist patterning and second photoresist patterning), which could ensure the accuracy and consistency of solder filling and improve the packaging efficiency and reliability. Thirdly, photoresist was used in the preparation of three-dimensional optical structures (two-photon lithography). The utilizes photosensitive polymers (a type of photoresist) was used by two-photon lithography technology to fabricate three-dimensional waveguide structures in the packaging process of optoelectronic chip. Finally, photoresist was used in the optimization of grating couplers packaging technology. Photoresist was used for patterning the grating structure to achieve efficient coupling of optical signals in the grating packaging technology developed by Peking University Yangtze River Delta Institute of Optoelectronics, which had the characteristics of low loss designing and multi material compatibility.

For the formation of RDL layer, the architecture of photoresist used in FOPLP technology was showed in Figure 11. The Cu layer without patterning was formed by a plating process on whole surface of wafer, then a lithography was taken out on the Cu layer with forming a patterning PR layer. A wet etching process was introduced to form the patterning Cu layer. During the wet etch process, the area without opening of the PR layer could prevent the below Cu layer form being removed, and the Cu layer under the area of PR layer with opening was removed. Finally, the pattering PR layer was removed for forming the patterning RDL layer.

5.5 Methods to guarantee the stability of organic packaging materials

As known, the requirements in current processes of IC packaging increase higher and more stringent standards, so how to ensure the stability of organic packaging materials will be a key issue in the future.^[75-77] Combining multiple aspects such as production, transportation, storage and usage, we give a few suggestions to guarantee the stability of organic packaging materials, which are listed as below: First, it is recommended that material manufacturer can not replace the production sites, production equipment and pipelines as soon as possible. If it is necessary to change the production site due to objective reasons, it is necessary to report and communicate with the material customer. The customer needs to conduct relevant verification on the first few batches of organic packaging materials produced in the new site to ensure material stability (compared to materials produced in the old site). Second, material manufacturer needs to test the basic characteristics of organic packaging materials (such as viscosity, solid content, film-forming properties, modulus, tensile strength, mechanical strength and other parameters which customer is concerned about) after completing each batch of material production and before shipment. Third, organic packaging materials must be stored and transported strictly in accordance with relevant requirements (temperature, humidity, stacking method, packaging, light avoidance, etc.) during transportation. If any abnormal situations occur during transportation, they must be promptly counted and reported. Fourth, before receiving each batch of materials for storage, material customers must conduct a strict inspection of the material packaging (for any damage, dirt, etc.). During the storage process in the warehouse, the relevant conditions (temperature, humidity, stacking method, packaging, light avoidance, etc.) should be strictly set in accordance with relevant regulations. Finally, it is necessary to ask experienced employees to identify the basic characteristics of the materials (viscosity, fluidity, color, etc.) before using each batch of materials. The usage method must strictly follow the established operating method without any innovations.