Moore’s Law has been a major driving force for the exponential growth in the semiconductor industry for nearly the past six decades, regularly doubling the number of transistors on a chip and increasing performance twofold approximately every two years. In recent years, there have been position papers predicting the imminent demise of Moore’s Law as many physical limits are reached, mainly as a result of decades of aggressive technology scaling, lithography, non-scaling interconnection with technology nodes, random and systematic process variabilities, and more. Yet, the global semiconductor market size reached USD 513 billion in 2019 and is projected to reach USD 727 billion by 2027 on a CAGR of 4.7%. This projected growth can be attributed to the increasing consumption of consumer electronic devices globally as well as the emergence of big data, artificial intelligence, machine learning, internet of things, and 5G that provide tremendous new opportunities to the market growth. To sustain the semiconductor industry’s continued growth, however, the continuation of Moore’s Law or its variants must be realized which in turn requires unprecedented parallel R&D efforts on novel transistor architecture, new materials, efficient computational lithography, design and technology co-optimization, advanced packaging, and effective manufacturing yield improvement, etc.
Facing the ever more complex and challenging development of process technologies in the nanometer regime, advanced computer-aided design (CAD) technologies have become indispensable enablers for early pathfinding, transistor and backend definition and optimization, design & technology co-optimization for performance-power-area and reducing the risk in re-design, novel material exploration, lithography and OPC development, defect detection and yield improvement, etc. It is our great pleasure to present this special issue of the Journal of Microelectronic Manufacturing on “CAD Technologies Enabling Advanced Process Technology Development and Product Design.” This issue contains nine invited papers authored by distinguished scholars and researchers from leading universities, research institutes, and the industry. The topics covered include: (a) an industry-standard physical Spice model for FinFET to Gate-All-Around FET; (b) three Technology CAD (TCAD) device simulation papers discussing the Scharfetter-Gummel discretization scheme in solving the drift-diffusion transport model, an advanced open-source TCAD simulation platform, and a 1st principle-based TCAD simulation applied to the design of tunnel FET; (c) two papers on computational lithography and OPC utilizing machine learning; (d) one paper on TCAD-based methodology to enable design-technology co-optimization of advanced semiconductor memories including a multi-stage simulation flow to study the device-to-circuit performance in presence of statistical and process variability; (e) one paper on applications involving a complex set of material modeling tools and methodologies and share a perspective of the future of the area; and (f) one paper on a comprehensive pattern centric platform for process technology development and manufacturing.
We would like to express our sincerest gratitude to the authors for their gracious and insightful responses to our invitation to contribute to this special issue of JoMM. We sincerely appreciate their time, effort and support. Also, we would like to thank all the reviewers for their meticulous review and expert suggestions.